A common problem encountered by digital inputs on semiconductor integrated circuit chips involves the state of the digital inputs when the chip is powered up. If the digital inputs are floated the tendency of the digital inputs is to have a voltage value that is near some mid-rail value of voltage. This causes the input circuit to draw a significant level of current.
For example, FIG. 1 illustrates a graph of current versus time that shows the amount of current that flows in a typical Complementary Metal Oxide Semiconductor (CMOS) input circuit if the input is floated. As shown in FIG. 1, the value of the current rises in a short time from a value of zero to approximately three hundred micro-Amperes (300 μA). An integrated circuit chip that has many digital inputs can easily be leaking three hundred micro-Amperes (300 μA) for each digital input. In an environment in which low power consumption is required this amount of leakage is unacceptable.
A typical prior art method for handling this problem is to place a pull-down resistor on the input. FIG. 2 illustrates a prior art floating CMOS input circuit 200 in which the digital input is allowed to float. The leakage current versus time that is shown in the graph of FIG. 1 is the current flowing through the drain of the n-channel transistor N2 shown in FIG. 2. That is why the leakage current is identified as ID(N2) for N2 drain current.
A typical prior art pull-down resistor R1 is illustrated in FIG. 3. The circuit that is shown in FIG. 3 is the same circuit that is shown in FIG. 2 except that the pull-down resistor R1 has been placed on the input in parallel with n-channel transistor N2.
The presence of pull-down resistor R1 ensures that if the input voltage (Vin) is not driven, then the pull-down resistor R1 will pull the input voltage to a hard ground. This will prevent current leakage between p-channel transistor P2 and n-channel transistor N1.
There are two drawbacks to this prior art approach. The first drawback is that a pull-down resistor would have to be provided to every input circuit that would potentially be a floating CMOS input circuit. This would very likely be impractical for many circuits. The second drawback is that if the input voltage (Vin) experiences a high value of voltage (e.g., 3.3 volts), then the input would draw approximately one hundred sixty micro-Amperes (160 μA) from whatever source is driving the input voltage (Vin). This level of current consumption is to be avoided in a low power circuit design.
The prior art approach discussed above is inefficient because it requires a pull-down resistor for every floating input and because it generates too much current consumption for a low power consumption circuit. Therefore, it would be advantageous to have a more efficient system and method for providing a floating CMOS input circuit in a semiconductor integrated circuit chip.
Before undertaking the Detailed Description of the Invention below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patient document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior uses, as well as future uses, of such defined words and phrases.